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Features
* 16-Mbit Flash and 2-Mbit/4-Mbit SRAM * Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package * 2.7V to 3.3V Operating Voltage
Flash
* 2.7V to 3.3V Read/Write * Access Time - 85 ns * Sector Erase Architecture * * * *
- Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout - Eight 4K Word (8K Byte) Sectors with Individual Write Lockout Fast Word Program Time - 20 s Fast Sector Erase Time - 300 ms Dual-plane Organization, Permitting Concurrent Read While Program/Erase - Memory Plane A: Eight 4K Word and Seven 32K Word Sectors - Memory Plane B: Twenty-four 32K Word Sectors Erase Suspend Capability - Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 30 mA Active - 10 A Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Accelerated Program/Erase Operations RESET Input for Device Initialization Sector Lockdown Support Top/Bottom Block Configuration 128-bit Protection Register
* * * * * * *
16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory AT52BR1672(T) AT52BR1674(T) Preliminary
SRAM
* * * * * *
2-megabit (128K x 16)/4-megabit (256K x 16) 2.7V to 3.3V V CC Operating Voltage 70 ns Access Time Fully Static Operation and Tri-state Output 1.2V (Min) Data Retention Industrial Temperature Range
Device Number AT52BR1672(T) AT52BR1674(T)
Flash Plane Architecture 12M + 4M 12M + 4M
Flash Configuration 16M (1M x 16) 16M (1M x 16)
SRAM Configuration 2M (128K x 16) 4M (256K x 16)
Rev. 2604B-STKD-09/02
1
CBGA Top View
1 2 3 4 5 6 7 8 9 10 11 12 A
NC NC NC A11 A15 A14 A13 A12 GND NC NC NC
B
A16 A8 A10 A9 I/O15 SWE I/O14 I/O7
C
WE RDY BUSY I/O13 I/O6 I/O4 I/O5
D
SGND RESET I/O12 SCS2 SVcc Vcc
E
NC Vpp A19 I/O11 I/O10 I/O2 I/O3
F
SLB SUB SOE I/O9 I/O8 I/O0 I/O1
G
A18 A17 A7 A6 A3 A2 A1 SCS1
H
NC NC NC A5 A4 A0 CE GND OE NC NC NC
Pin Configurations
Pin Name A0 - A16 A0 - A17 A18 - A19 CE OE/SOE WE/SWE VCC VPP I/O0-I/O15 SCS1, SCS2 RDY/BUSY SVCC GND/SGND SUB SLB NC RESET
Function Flash/SRAM Common Address Input for 2M SRAM Flash/SRAM Common Address Input for 4M SRAM Flash Address Input Flash Chip Enable Flash/SRAM, Output Enable Flash/SRAM, Write Enable Flash Power Supply Optional Flash Power Supply for Faster Program/Erase Operations Data Inputs/Outputs SRAM Chip Select Flash Ready/Busy Output SRAM Power Supply Flash/SRAM GND SRAM Upper Byte SRAM Lower Byte No Connect Flash Reset
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AT52BR1672(T)/1674(T)
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AT52BR1672(T)/1674(T)
Description
The AT52BR1672(T) combines a 16-megabit Flash (1M x 16) and a 2-megabit SRAM (organized as 128K x 16) in a stacked CBGA package; while the AT52BR1674(T) combines a 16megabit Flash (1M x 16) and a 4-megabit SRAM (organized as 256K x 16) in a stacked CBGA package. Both devices operate at 2.7V to 3.3V in the industrial temperature range. The modules use a 16-megabit Flash with dual plane architecture for concurrent read/write operations. The Flash is organized as 12M + 4M for planes B and A, respectively.
Block Diagram
ADDRESS OE WE SOE SWE
RESET CE FLASH RDY/BUSY SRAM SCS1
DATA
Absolute Maximum Ratings
Temperature under Bias .................................. -40C to +85C Storage Temperature ..................................... -55C to +150C All Input Voltages except VPP and RESET (including NC Pins) with Respect to Ground .....................................-0.2V to +3.3V Voltage on VPP with Respect to Ground ..................................-0.2V to + 6.25V Voltage on RESET with Respect to Ground ...................................-0.2V to +13.5V All Output Voltages with Respect to Ground .....................................-0.2V to +0.2V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC Operating Range
AT52BR1672(T)/1674(T) Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 2.7V to 3.3V
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16-megabit Flash Description
The 16-megabit Flash memory organized as 1,048,576 words of 16 bits each. The x16 data appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations.The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see Sector Lockdown section). The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend feature. This feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. There is no reason to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an erase cycle is detected by the Ready/Busy pin, Data Polling or by the toggle bit. The VPP pin provides faster program/erase times. With VPP at 5.0V or 12.0V, the program and erase operations are accelerated. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to V CC. Erase and Erase Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.
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AT52BR1672(T)/1674(T)
16-megabit Flash Memory Block Diagram
I/O0 - I/O15
OUTPUT BUFFER
INPUT BUFFER
OUTPUT MULTIPLEXER
A0 - A19
INPUT BUFFER
STATUS REGISTER
DATA REGISTER
IDENTIFIER REGISTER
CE COMMAND REGISTER WE OE RESET
ADDRESS LATCH DATA COMPARATOR
RDY/BUSY WRITE STATE MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE VOLTAGE SWITCH
VPP
VCC GND X-DECODER
PLANE B SECTORS
PLANE A SECTORS
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Device Operation
READ: The 16-megabit Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a section is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 s. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. VPP PIN: The circuitry of the 16-megabit Flash is designed so that the device can be programmed or erased from the VCC power supply or from the VPP input pin. When VPP is less than or equal to the VCC pin, the device selects the V CC supply for programming and erase
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operations. When the VPP pin is greater than the V CC supply, the device will select the V PP input as the power supply for programming and erase operations. The device will allow for some variations between the VPP input and the VCC power supply in its selection of VCC or VPP for program or erase operations. If the VPP pin is within 0.3V of VCC for 2.7V < VCC < 3.3V, then the program or erase operations will use VCC and disregard the VPP input signal. When the VPP signal is used to accelerate program and erase operations, the VPP must be in the 5V 0.5V or 12V 0.5V range to ensure proper operation. The Vpp pin can be left unconnected. SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector's usage as a write protected region is optional to the user. At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. Since this device has a dual-plane architecture, there is no need to use the Erase Suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address (determined by A18 and A19). The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see "Operating Modes" on page 13 (for hardware operation) or "Software Product Identification Entry/Exit" on page 21. The manufacturer and device codes are the same for both modes.
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128-BIT PROTECTION REGISTER: The 16-megabit Flash contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition table on page 9. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don't cares. Please see the "Protection Register Addressing Table" on page 10 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After reading the protection register, the Product ID Exit command must be given prior to performing any other operation. DATA POLLING: The Flash features Data Polling to indicate the end of a program cycle. During a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see "Status Bit Table" on page 22 for more details. TOGGLE BIT: In addition to Data Polling, the 16-megabit Flash provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle bit that is available on I/O6. While a sector is erase suspended, a read or a program operation from the suspended sector will result in the I/O2 bit toggling. Please see "Status Bit Table" on page 22 for more details. RDY/BUSY: For the 16-megabit Flash, an open-drain Ready/Busy output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY line. HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against inadvertent programs to the Flash in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. OUTPUT LEVELS: For the 16-megabit Flash, output high levels (VOH) are equal to V CCQ 0.2V (not VCC). For 2.7V - 3.3V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ must be regulated to 2.0V 10%, while VCC must be regulated to 2.7V - 3.0V (for minimum power).
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AT52BR1672(T)/1674(T)
Command Definition in Hex(1)
Command Sequence Read Chip Erase Sector Erase Word Program Enter Single Pulse Program Mode Single Pulse Word Program Sector Lockdown Erase Suspend Erase Resume Product ID Entry Product ID Exit(6) Product ID Exit(6) Program Protection Register Lock Protection Register - Block B Status of Block B Protection Bus Cycles 1 6 6 4 6 1 6 1 1 3 3 1 4 4 4 1st Bus Cycle Addr Addr 555 555 555 555 Addr 555 XXX PA(5) 555 555 XXX 555 555 555 Data DOUT AA AA AA AA DIN AA B0 30 AA AA F0 AA AA AA AAA AAA AAA 55 55 55 555 555 555 C0 C0 90 Addr 080 80 DIN X0 DOUT(7) AAA AAA 55 55 555 555 90 F0 AAA 55 555 80 555 AA AAA 55 SA(3)(4) 60 AAA (2) AAA AAA AAA 55 55 55 55 555 555 555 555 80 80 A0 80 555 555 Addr 555 AA AA DIN AA AAA 55 555 A0 AAA AAA 55 55 555 SA(3)(4) 10 30 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don't Care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don't Care. 2. Since A11 is a Don't Care, AAA can be replaced with 2AA. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see page 11 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. PA is the plane address (A19-A18). 6. Either one of the Product ID Exit commands can be used. 7. If data bit D1 is "0", block B is locked. If data bit D1 is "1", block B can be reprogrammed.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and VPP with Respect to Ground ...................................-0.6V to +13.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Protection Register Addressing Table
Word 0 1 2 3 4 5 6 7 Note: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0
1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - A8 = 0.
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AT52BR1672(T)/1674(T)
Top Boot 16-megabit Flash (12M + 4M) - Sector Address Table
x16 Plane B B B B B B B B B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K Address Range (A19 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - F8FFF F9000 - F9FFF FA000 - FAFFF FB000 - FBFFF FC000 - FCFFF FD000 - FDFFF FE000 - FEFFF FF000 - FFFFF
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Bottom Boot 16-megabit Flash (12M + 4M) - Sector Address Table
x16 Plane A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B B B B B B Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A19 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - F7FFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF
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DC and AC Operating Range
AT52BR1672(T)-85 Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 2.7V to 3.3V AT52BR1674(T)-85 -40C - 85C 2.7V to 3.3V
Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X X
RESET VIH VIH VIH VIH VIH VIH VIL
VPP X VPP(6) X X X X X
Ai Ai Ai X
I/O DOUT DIN High-Z
Standby/Program Inhibit Program Inhibit
X VIL VIH X
X Output Disable Reset Product Identification Hardware VIL X X
High-Z X High-Z
VIL
VIH
VIH
A1 - A19 = V IL, A9 = V H(3), A0 = V IL A1 - A19 = VIL, A9 = V H(3), A0 = V IH A0 = VIL, A1 - A19 = VIL A0 = VIH, A1 - A19 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
VIH
Notes:
1. 2. 3. 4. 5. 6.
X can be VIL or VIH. Refer to AC programming waveforms on page 18. VH = 12.0V 0.5V. Manufacturer Code: 001FH. Device Code: 00C2H (Top Boot); 00C0H (Bottom Boot). See details under "Software Product Identification Entry/Exit" on page 21. VPP can be left unconnected or 0V VPP 3.3V. For faster erase/program operations, VPP can be set to 5.0V 0.5V or 12V 0.5V.
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DC Characteristics
Symbol ILI ILO ISB1 ISB2 ISB3 ICC
(1)(2)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Standby Current TTL VCC Active Read Current VCC Programming Current (VPP = VCC ) VPP Input Load Current VCC Programming Current (VPP = 5.0V 0.5V) VPP Programming Current (VPP = 5.0V 0.5V) VCC Programming Current (VPP = 12.0V 0.5V) VPP Programming Current (VPP = 12.0V 0.5V) Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to V CC CE = 2.0V to VCC CE = 2.0V to VCC, VCC = 2.85V f = 5 MHz; IOUT = 0 mA, 3.3V V CC
Min
Max 10 10 10 1 10 30 45
Units A A A mA A mA mA A A mA mA mA mA V V
ICC1 IPP1 ICC2 IPP2 ICC3 IPP3 VIL VIH VOL1 VOL2 VOH1 VOH2
VPP = 0V, VCC = 3.0V VPP = VCC = 3.0V
10 10 40 5 40 6 0.6 2.0
IOL = 2.1 mA IOL = 1.0 mA IOH = -400 A IOH = -400 A IOH = -100 A IOH = -100 A VCCQ < 2.6V VCCQ 2.6V VCCQ < 2.6V VCCQ 2.6V V CCQ - 0.2 2.4 V CCQ - 0.1 2.5
0.45 0.20
V V V V V V
Output High Voltage
Notes:
1. In the erase mode, ICC is 50 mA. 2. For 3.3V < VCC < 3.6V, ICC (max) = 35 mA.
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AC Read Characteristics
AT52BR1672(T)-85 Symbol tACC tCE
(1) (2)
AT52BR1674(T)-85 Min Max 85 85 0 0 0 40 25 Units ns ns ns ns ns 100 ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first RESET to Output Delay
Min
Max 85 85
tOE
0 0 0
40 25
tDF(3)(4) tOH tRO
100
AC Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID
CE
tCE OE tOE tDF tACC tOH
RESET HIGH Z
tRO OUTPUT VALID
OUTPUT
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
15
2604B-STKD-09/02
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
16
AT52BR1672(T)/1674(T)
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AT52BR1672(T)/1674(T)
AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Write Pulse Width High Min 0 40 0 0 40 30 0 30 Max Units ns ns ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
CE Controlled
17
2604B-STKD-09/02
Program Cycle Characteristics
Symbol tBP tBPVPP tAS tAH tDS tDH tWP tWPH tWC tSR/W tRP tRH tEC tECVPP tSEC tEPS Parameter Word Programming Time (0V < VPP < 4.5V) Word Programming Time (VPP > 4.5V) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Write Cycle Time Latency between Read and Write Operations Reset Pulse Width Reset High Time before Read Chip Erase Cycle Time (VPP < 4.5V) Chip Erase Cycle Time (VPP > 4.5V) Sector Erase Cycle Time (VPP < 4.5V) Erase or Program Suspend Time 300 0 40 30 0 40 30 70 50 500 50 12 6 400 15 Min Typ 20 10 Max 50 25 Units s s ns ns ns ns ns ns ns ns ns ns seconds seconds ms s
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
t
tAS
tAH
555 AAA
tDH
555 ADDRESS
SR/W
A0 - A19
VALID READ ADDRESS
tWC
tDS
tACC AA 55 A0 INPUT DATA OUTPUT DATA
DATA
18
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
Sector or Chip Erase Cycle Waveforms
OE (1) CE
tWP tWPH t EC
WE
tSR/W tAS tAH
555 AAA
tDH
555 555 AAA Note 2 ADDRESS VALID
A0 - A19
tWC
tDS
AA 55 80 AA 55 Note 3 OUTPUT VALID
DATA
Notes:
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
t ACC
1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
19
2604B-STKD-09/02
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 15.
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in "AC Read Characteristics" on page 15. 50 0 Min 10 10 Typ Max Units ns ns ns ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
20
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 555
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 555
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 90 TO ADDRESS 555
LOAD DATA 80 TO ADDRESS 555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 555
Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS AAA
LOAD DATA 55 TO ADDRESS AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA 60 TO SECTOR ADDRESS
LOAD DATA F0 TO ADDRESS 555
PAUSE 200 s(2)
Notes:
EXIT PRODUCT IDENTIFICATION MODE(4)
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex) and A11 - A19 (Don't Care). 2. Sector Lockdown feature enabled.
Notes:
1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex) and A11 - A19 (Don't Care). 2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. Additional Device Code is read for address 0003H 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH. Device Code: 00C2H (Top Boot); 00C0H (Bottom Boot). Additional Device Code: 00C8H. 6. Either one of the Product ID Exit commands can be used.
21
2604B-STKD-09/02
Status Bit Table
Status Bit I/O7 Read Address In While Plane A Plane B Plane A I/O6 Plane B Plane A I/O2 Plane B
Programming in Plane A Programming in Plane B
I/O7 DATA
DATA I/O7
TOGGLE DATA
DATA TOGGLE
1 DATA
DATA 1
Erasing in Plane A Erasing in Plane B
0 DATA
DATA 0
TOGGLE DATA
DATA TOGGLE
TOGGLE DATA
DATA TOGGLE
Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector
1 DATA
1 DATA
1 DATA
1 DATA
TOGGLE DATA
TOGGLE DATA
Erase Suspended & Program Non-erasing Sector in Plane A Erase Suspended & Program Non-erasing Sector in Plane B
I/O7
DATA
TOGGLE
DATA
TOGGLE
DATA
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
22
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
2-megabit SRAM Description Features
* Fully Static Operation and Tri-state Output * TTL Compatible Inputs and Outputs * Battery Backup
- 1.2V (Min) Data Retention
The 2-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 128K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly well-suited for the high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
Voltage (V) 2.7 - 3.3
Speed (ns) 70
Operation Current/ICC (mA) (Max) 10
Standby Current (A) (Max) 10
Temperature (C) -40 - 85
Block Diagram
A0 ROW DECODER SENSE AMP I/O0
DATA I/O BUFFER
BLOCK DECODER
PRE DECODER
ADD INPUT BUFFER
I/O7 I/O8
MEMORY ARRAY 512K X 16 WRITE DRIVER
COLUMN DECODER
I/O15
A16
SCS1 SCS2 SOE SLB SUB SWE
23
2604B-STKD-09/02
Absolute Maximum Ratings(1)
Symbol VIN, VOUT VCC TA TSTG PD Note: Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Rating -0.3 to 3.6 -0.3 to 4.6 -40 to 85 -55 to 150 1.0 Unit V V C C W
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Truth Table
I/O Pin SCS1 H(1) X X
(1)
SCS2 X
SWE
SOE
SLB X
(2)
SUB X
(2)
Mode
I/O0 - I/O7
I/O8 - I/O15
Power
L X
X
X H L H H L L H L L H L L
Deselected
High-Z
High-Z
Standby
L(1)
H
H
H
H L L
Output Disabled
High-Z
High-Z
Active
DIN Write High-Z DIN DOUT Read High-Z DOUT
High-Z DIN DIN High-Z DOUT DOUT Active Active
L
H
L
X
H L L
L
H
H
L
H L
Notes:
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH) 2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is LOW, data is written or read to the lower byte, I/O0 - I/O8. When SUB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
Recommended DC Operating Condition
Symbol VCC VSS VIH VIL(1) Note: Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min 2.3 0 2.2 -0.2(1) Typ 3.0 0 Max 3.3 0 VCC + 0.3 0.4 Unit V V V V
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
24
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
DC Electrical Characteristics
TA = -40C to 85C
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VSS < VIN < VCC VSS < VOUT < VCC, SCS1 = VIH or SCS2=VIL or SOE = V IH or SWE = VIL or SUB = VIH, SLB = VIH SCS1 = VIL, SCS2=V IH, VIN = V IH or VIL, II/O = 0 mA Cycle Time = 1 s II/O = 0 mA, SCS1 = 0.2V, SCS2 = VCC -0.2V, VIN 0.2V or V IN VCC - 0.2V Cycle Time = Min, 100% Duty, II/O = 0 mA SCS1 = VIL, SCS2 = VIH, VIN = V IH or VIL ISB ISB1 Standby Current (TTL Input) Standby Current (CMOS Input) SCS1 = VIH or SCS2 = VIL SCS1 VCC - 0.2V or SCS2 VSS + 0.2V IOL = 0.5 mA IOH = -0.5 mA 2.0 LL SL 0.4 Min -1 -1 Typ(1) Max 1 1 Unit A A
ICC ICC1
Operating Power Supply Current Average Operating Current
5 4
10 6
mA mA
30
45
mA
0.5 10 2 0.4
mA A A V V
VOL VOH Note:
Output Low Output High
1. Typical values are at VCC = 3.0V, TA = 25C. Typical values are not 100% tested.
Capacitance(1)
(Temp = 25C, f = 1.0 MHz)
Symbol CIN COUT Note: Parameter Input Capacitance (Add, SCS1, SCS2, SLB, SUB, SWE, SOE) Output Capacitance (I/O) Condition VIN = 0 V VI/O = 0 V Max 8 10 Unit pF pF
1. These parameters are sampled and not 100% tested.
25
2604B-STKD-09/02
AC Characteristics
TA = -40C to 85C, Unless Otherwise Specified
70 ns # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol tRC tAA tACS tOE tBA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tOH tWC tCW tAW tBW tAS tWP tWR tWHZ tDW tDH tOW Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid SLB, SUB Access Time Chip Select to Output in Low Z Output Enable to Output in Low Z SLB, SUB Enable to Output in Low Z Chip Deselection to Output in High Z Out Disable to Output in High Z SLB, SUB Disable to Output in High Z Output Hold from Address Change Write Cycle Time Chip Selection to End of Write Address Valid to End of Write SLB, SUB Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 5 0 0 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 25 30 30 30 Min 70 70 70 35 35 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Test Conditions
TA = -40C to 85C, Unless Otherwise Specified
Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load Value 0.4V to 2.2V 5 ns 1.5V CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
26
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
Output Test Load
Timing Diagrams
Read Cycle 1(1),(4)
tRC ADDRESS tAA tACS SCS1 tOH
SCS2 tBA SUB, SLB tOE SOE tOLZ(3) tBLZ(3) DATA OUT HIGH-Z tCLZ(3) DATA VALID tOHZ (3) tBHZ(3) tCHZ(3)
Read Cycle 2(1),(2),(4)
tRC ADDRESS tAA tOH DATA OUT
PREVIOUS DATA DATA VALID
tOH
Read Cycle 3(1),(2),(4)
SCS1 SUB, SLB
SCS2
tACS tCLZ (3)
DATA VALID
tCHZ (3)
DATA OUT
Notes:
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active status. 2. SOE = VIL. 3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
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2604B-STKD-09/02
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tCW tWR(2)
SCS1
SCS2
tAW tBW
SUB, SLB
tWP
SWE
tAS tDW DATA VALID tWHZ(3)(7) tOW
(5) (5)
tDH
DATA IN
HIGH-Z
tAS
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tAS tCW tWR(2)
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW tDH HIGH-Z
DATA IN
DATA VALID HIGH-Z
DATA OUT
Notes:
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB. 2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after the SWE transition, outputs remain in a high impedance state. 5. Q (data out) is the same phase with the write data of this write cycle. 6. Q (data out) is the read data of the next address. 7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
28
AT52BR1672(T)/1674(T)
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AT52BR1672(T)/1674(T)
Data Retention Electric Characteristic
TA = -40C to 85C
Symbol VDR Parameter VCC for Data Retention Test Condition SCS1 > V CC -0.2V, SCS2 0.2V or VCC - 0.2V, VSS VIN VCC VCC = 3.0V, SCS1 > V CC - 0.2V or SCS2 VSS + 0.2V or VSS VIN VCC 0 See Data Retention Timing Diagram tRC(2) ns Min 1.2 Typ Max 3.3 Unit V
ICCDR
Data Retention Current
9.5 0.4(1) 0.7
A A ns
tCDR tR Notes:
Chip Deselect to Data Retention Time Operating Recovery Time
1. Typical values are under the condition of TA = 25C. Typical values are sampled and not 100% tested. 2. tRC is read cycle time.
Data Retention Timing Diagram 1
VCC 2.3V tCDR
DATA RETENTION MODE
tR
IH VDR
SCS1 > VCC - 0.2V
SCS1 VSS
Data Retention Timing Diagram 2
VCC 2.3V SCS2 VDR tCDR
DATA RETENTION MODE
tR
0.4V VSS
SCS2 < 0.2V
29
2604B-STKD-09/02
4-megabit SRAM Description Features
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K words by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for high-speed and low-power circuit technology. It is particularly well-suited for the high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
* Fully Static Operation and Tri-state Output * TTL Compatible Inputs and Outputs * Battery Backup
- 1.2V (Min) Data Retention
Voltage (V) 2.7 - 3.3
Speed (ns) 70
Operation Current/ICC (mA) (Max) 5
Standby Current (A) (Max) 15
Temperature (C) -40 - 85
Block Diagram
A0 ROW DECODER SENSE AMP I/O0
DATA I/O BUFFER
BLOCK DECODER
PRE DECODER
ADD INPUT BUFFER
I/O7 I/O8
MEMORY ARRAY 256K X 16 WRITE DRIVER
COLUMN DECODER
I/O15
A17
SCS1 SCS2 SOE SLB SUB SWE
30
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
Absolute Maximum Ratings(1)
Symbol VIN, VOUT VCC TA TSTG PD Note: Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Rating -0.3 to 3.6 -0.3 to 4.6 -40 to 85 -55 to 150 1.0 Unit V V C C W
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Truth Table
I/O Pin SCS1 H(1) X(1) X SCS2 X X L X X X H L L(1) H H H H L L H L H L X L L H L H H L L Notes: L L H L Read DOUT DOUT H H L L H L Write DIN DIN DOUT High-Z DIN High-Z High-Z DIN DIN High-Z High-Z DOUT DOUT High-Z Active Active Output Disabled High-Z High-Z Active X Deselected High-Z High-Z Standby SWE SOE SLB
(2)
SUB
(2)
Mode
I/O0 - I/O7
I/O8 - I/O15
Power
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH) 2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8 - I/O15.
Recommended DC Operating Condition
Symbol VCC VSS VIH VIL
(1)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage
Min 2.7 0 2.2 -0.31
(1)
Typ 3.0 0
Max 3.3 0 VCC + 0.3 0.6
Unit V V V V
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
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2604B-STKD-09/02
DC Electrical Characteristics
TA = -40C to 85C
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition VSS < VIN < VCC VSS < VOUT < VCC, SCS1 = VIH or SCS2=VIL or SOE = V IH or SWE = VIL or SUB = VIH, SLB = VIH SCS1 = VIL, SCS2=V IH, VIN = V IH or VIL, II/O = 0 mA SCS1 = VIL, SCS2 = VIH, VIN = V IH or VIL, Cycle Time = Min 100% Duty, II/O = 0 mA SCS1 < 0.2V, SCS2 > VCC - 0.2V VIN < 0.2V or VIN > V CC - 0.2V, Cycle Time = 1 s 100% Duty, II/O = 0 mA ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or SUB, SLB = VIH VIN = V IH or VIL SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > V CC - 0.2V or VIN < V SS + 0.2V IOL = 0.1 mA IOH = -0.1 mA 2.4 SL Min -1 -1 Max 1 1 Unit A A
ICC ICC1
Operating Power Supply Current Average Operating Current
5 35
mA mA
5
mA
0.5
mA
ISB1
Standby Current (CMOS Input)
4
A
LL
15
A
VOL VOH
Output Low Output High
0.4
V V
Capacitance(1)
(Temp = 25C, f = 1.0 MHz)
Symbol CIN COUT Note: Parameter Input Capacitance (Add, SCS1, SCS2, SLB, SUB, SWE, SOE) Output Capacitance (I/O) Condition VIN = 0 V VI/O = 0 V Max 8 10 Unit pF pF
1. These parameters are sampled and not 100% tested.
32
AT52BR1672(T)/1674(T)
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AT52BR1672(T)/1674(T)
AC Characteristics
TA = -40C to 85C, Unless Otherwise Specified
70 ns # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol tRC tAA tACS tOE tBA tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tOH tWC tCW tAW tBW tAS tWP tWR tWHZ tDW tDH tOW Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid SLB, SUB Access Time Chip Select to Output in Low Z Output Enable to Output in Low Z SLB, SUB Enable to Output in Low Z Chip Deselection to Output in High Z Out Disable to Output in High Z SLB, SUB Disable to Output in High Z Output Hold from Address Change Write Cycle Time Chip Selection to End of Write Address Valid to End of Write SLB, SUB Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10 5 10 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 20 30 30 30 Min 70 70 70 35 70 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Test Conditions
TA = -40C to 85C, Unless Otherwise Specified
Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load Value 0.4V to 2.2V 5 ns 1.5V CL = 5 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
33
2604B-STKD-09/02
Output Test Load
Timing Diagrams
Read Cycle 1(1),(4)
tRC ADDRESS tAA tACS SCS1 tOH
SCS2 tBA SUB, SLB tOE SOE tOLZ(3) tBLZ(3) DATA OUT HIGH-Z tCLZ(3) DATA VALID tOHZ (3) tBHZ(3) tCHZ(3)
Read Cycle 2(1),(2),(4)
tRC ADDRESS tAA tOH DATA OUT
PREVIOUS DATA DATA VALID
tOH
Read Cycle 3(1),(2),(4)
SCS1 SUB, SLB
SCS2
tACS tCLZ (3)
DATA VALID
tCHZ (3)
DATA OUT
Notes:
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active status. 2. SOE = VIL. 3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
34
AT52BR1672(T)/1674(T)
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AT52BR1672(T)/1674(T)
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tCW tWR(2)
SCS1
SCS2
tAW tBW
SUB, SLB
tWP
SWE
tAS tDW DATA VALID tWHZ(3)(7) tOW
(5) (5)
tDH
DATA IN
HIGH-Z
tAS
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tAS tCW tWR(2)
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW tDH HIGH-Z
DATA IN
DATA VALID HIGH-Z
DATA OUT
Notes:
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB. 2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after the SWE transition, outputs remain in a high impedance state. 5. Q (data out) is the same phase with the write data of this write cycle. 6. Q (data out) is the read data of the next address. 7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active.
35
2604B-STKD-09/02
Data Retention Electric Characteristic
TA = -40C to 85C
Symbol VDR Parameter VCC for Data Retention Test Condition SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V Vcc=1.5V, SCS1 > VCC - 0.2V or SCS2 < VSS + 0.2V or SUB, SLB > VCC - 0.2V VIN > VCC - 0.2V or VIN < VSS + 0.2V See Data Retention Timing Diagram tRC(2) ns SL Min 1.2 Typ(1) Max 3.3 Unit V
ICCDR
Data Retention Current
0.1
2
A
LL
0.1
10
A
tCDR tR Note:
Chip Deselect to Data Retention Time Operating Recovery Time 2. tRC is read cycle time.
0
ns
1. Typical values are under the condition of TA = 25C. Typical values are sampled and not 100% tested.
Data Retention Timing Diagram 1
VCC 2.7V tCDR
DATA RETENTION MODE
tR
IH VDR
SCS1 > VCC - 0.2V
SCS1 VSS
Data Retention Timing Diagram 2
VCC 2.7V SCS2 VDR tCDR
DATA RETENTION MODE
tR
0.4V VSS
SCS2 < 0.2V
36
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
AT52BR1672(T)/1674(T)
Ordering Information
tACC (ns) 85 85 85 85 Voltage Range 2.7V - 3.3V 2.7V - 3.3V 2.7V - 3.3V 2.7V - 3.3V Ordering Code AT52BR1672(T)-85CI AT52BR1674(T)-85CI AT52BR1672-85CI AT52BR1674-85CI Package 66C5 66C5 66C5 66C5 Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C) Industrial (-40 to 85C)
Package Type 66C5 66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
37
2604B-STKD-09/02
Package Drawing
66C5 - CBGA
E
0.12 C C Seating Plane
Marked A1 Identifier D
Side View
Top View
A1 A
0.60 REF
E1 e A1 Ball Corner 1.20 REF
A B C D E F G H
D1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL e
12 11 10 9 8 7 6 5 4 3 2 1
MIN 9.90 - 7.90 - - 0.25
NOM 10.00 8.80 8.00 5.60 - - 0.80 BSC
MAX 10.10 - 8.10 - 1.20 -
NOTE
E E1 D
Ob
Bottom View
D1 A A1 e Ob
-
0.40
-
09/19/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 66C5 REV. A
R
38
AT52BR1672(T)/1674(T)
2604B-STKD-09/02
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Microcontrollers
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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2604B-STKD-09/02 /0M

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